| US 7,581,144 B2 | ||
| Microprocessor and processing method thereof | ||
| Katsuyuki Kimura, Kamakura (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Nov. 20, 2006, as Appl. No. 11/561,672. | ||
| Claims priority of application No. 2005-339178 (JP), filed on Nov. 24, 2005. | ||
| Prior Publication US 2007/0198817 A1, Aug. 23, 2007 | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—45 [712/227] | 20 Claims |
| 1. A microprocessor comprising:
a processor module executing an instruction to generate trace information including the information of the kind and the length
of the instruction;
an application processing circuit operating in cooperation with the processor module to process a specific application;
an address calculating circuit calculating an execution address for executing the instruction based on the information of
the instruction length;
a data obtaining circuit obtaining data from the application processing circuit when the calculated execution address is located
within a range of a designated address; and
a trace memory in which the obtained data is stored together with the trace information.
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