| US 7,581,124 B1 | ||
| Method and mechanism for controlling power consumption of an integrated circuit | ||
| Neil G. Jacobson, Los Altos, Calif. (US); Matthew T. Murphy, San Jose, Calif. (US); Tim Tuan, San Jose, Calif. (US); Kameswara K. Rao, San Jose, Calif. (US); and Robert O. Conn, Laupahoehoe, Hi. (US) | ||
| Assigned to XILINX, Inc., San Jose, Calif. (US) | ||
| Filed on Jan. 04, 2006, as Appl. No. 11/326,542. | ||
| Application 11/326542 is a continuation in part of application No. 10/783589, filed on Feb. 20, 2004. | ||
| Application 10/783589 is a continuation in part of application No. 10/666669, filed on Sep. 19, 2003, granted, now 7,098,689. | ||
| Int. Cl. G06F 1/22 (2006.01) | ||
| U.S. Cl. 713—310 [713/300] | 18 Claims |
| 1. A system including an integrated circuit (IC) device, the IC device comprising:
a power rail to provide a supply voltage;
a plurality of logic blocks;
a plurality of gating circuits, each coupled between the power rail and a power terminal of a corresponding logic block and
having a control terminal to receive a corresponding control signal, wherein the gating circuits are configured to selectively
adjust an operating voltage provided to the logic blocks in response to the control signals;
a memory circuit for storing the control signals;
a test pin set to receive a test signal set comprising the control signals; and
a test circuit including a boundary scan register coupled to the test pin set and coupled to the memory circuit, wherein the
test circuit is configured to write the control signals received from the test pin set into the memory circuit,
wherein the test pin set does not receive data signals used to program the plurality of logic blocks.
|