| US 7,581,058 B2 | ||
| Non-volatile memory having multiple erase operations | ||
| Yoshinori Takase, Tokyo (Japan); Keiichi Yoshida, Takarazuka (Japan); Takashi Horii, Higashimurayama (Japan); Atsushi Nozoe, Hino (Japan); Takayuki Tamura, Higashiyamato (Japan); Tomoyuki Fujisawa, Takarazuka (Japan); and Ken Matsubara, Higashimurayama (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan); and Hitachi ULSI Systems Co., Ltd., Tokyo (Japan) | ||
| Filed on Dec. 24, 2007, as Appl. No. 11/963,913. | ||
| Application 11/963913 is a continuation of application No. 10/510150, granted, now 7,334,080, previously published as PCT/JP02/11953, filed on Nov. 15, 2002. | ||
| Claims priority of application No. PCT/JP02/03417 (WO), filed on Apr. 05, 2002. | ||
| Prior Publication US 2008/0098190 A1, Apr. 24, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 12/06 (2006.01) | ||
| U.S. Cl. 711—103 [711/102] | 3 Claims |
| 1. A nonvolatile memory structured on one semiconductor substrate, comprising:
a plurality of memory banks, each comprising a nonvolatile memory unit and a buffer unit;
a control circuit; and
an interface,
wherein the control circuit controls access to one or more of the plurality of memory banks in accordance with an arbitrary
one of a plurality of instructions received from outside via the interface,
wherein when receiving a first erase instruction, the control circuit performs one of a one block erase operation or a plural
block erase operation in response to whether one block is selected or plural blocks are selected before receiving the first
erase instruction, and
wherein when receiving a second erase instruction, the control circuit erases data stored in all of the buffer units of the
plurality of memory banks.
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