| US 7,581,055 B2 | ||
| Multiple processor system and method including multiple memory hub modules | ||
| Joseph M. Jeddeloh, Shoreview, Minn. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Dec. 18, 2007, as Appl. No. 12/2,849. | ||
| Application 12/002849 is a continuation of application No. 11/544352, filed on Oct. 05, 2006, granted, now 7,386,649. | ||
| Application 11/544352 is a continuation of application No. 10/653044, filed on Aug. 28, 2003, granted, now 7,136,958. | ||
| Prior Publication US 2008/0215792 A1, Sep. 04, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 13/00 (2006.01); G06F 13/28 (2006.01) | ||
| U.S. Cl. 710—317 [711/117; 711/170] | 11 Claims |
| 3. A memory system, comprising:
a plurality of memory requestors; and
a first rank of memory modules each of which comprise:
a plurality of memory devices; and
a memory hub comprising:
a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices in the
memory module;
a cross bar switch having a plurality of first switch ports, a plurality of second switch ports, and a plurality of memory
ports, each of the first switch ports being coupled to a respective one of the memory requesters, and each of the memory ports
being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each
of the memory requesters to any one of the memory controllers through a respective one of the first switch ports and to selectively
couple each of the memory requesters to any one of the second switch ports; and
a second rank of memory modules each of which comprise:
a plurality of memory devices; and
a memory hub comprising:
a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices in the
memory module; and
a cross bar switch having a plurality of third switch ports and a plurality of memory ports, each of the third switch ports
being coupled to one of the second switch ports in the memory hub in a respective one of the memory modules in the first rank,
and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable
to selectively couple each of the memory modules in the first plurality to any one of the memory controllers in the memory
hub.
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