	US 7,580,967 B2
	Processor with maximum and minimum instructions
Alexander Tessarolo, Sydney (Australia); Karthikeyan Rajan Madathil, Bangalore (India); and G. Subash Chandar, Tamil Nadu (India)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on Jan. 22, 2003, as Appl. No. 10/349,336.
Claims priority of provisional application 60/361025, filed on Feb. 28, 2002.
Prior Publication US 2003/0163499 A1, Aug. 28, 2003
Int. Cl. G06F 7/499 (2006.01)

U.S. Cl. 708—552

2 Claims

1. A computer implemented method of limiting a double length variable to a maximum value comprising the steps of:

storing a set of most significant bits of a maximum value in a first memory location;

storing a set of least significant bits of said maximum value in a second memory location;

storing a set of most significant bits of the double length variable in a first data register of a set of data registers;

storing a set of least significant bits of the double length variable in a second date register of said set of data registers;

a performing a first subtracting of said set of most significant bits of said maximum value stored in said first memory location from said set of most significant bits of said double length variable stored in said first data register in an arithmetic logic unit;

setting a zero flag within said arithmetic logic unit to 1 and setting a negative flag within said arithmetic logic unit to 0 if said first subtracting produces a zero result;

setting said zero flag to 0 if said first subtracting produces a non-zero result;

setting said negative flag to 1 if said first subtracting produces a less than zero result;

setting said negative flag to 0 if said first subtracting does not produce a less than zero result;

writing said set of most significant bits stored in said first memory location into said first data register if said first subtracting does not produce a less than zero result;

writing said set of least significant bits stored in said second memory location into said second data register if said negative flag is 0 and said zero flag is 0;

performing a second subtracting of said set of least significant bits of said maximum value stored in said second memory location from said set of least significant bits of said double length variable stored in said second data register in said arithmetic logic unit; and

writing said set of least significant bits stored in said second memory location into said second data register if said second subtracting produces a greater than zero result.