US 7,580,965 B2
Discrete-time convolution cycle reduction with programmable digital signal processor
Steven R. Jahnke, Tokyo (Japan)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on Sep. 27, 2002, as Appl. No. 10/256,588.
Prior Publication US 2004/0064494 A1, Apr. 01, 2004
Int. Cl. G06F 17/15 (2006.01); G06F 17/10 (2006.01)
U.S. Cl. 708—420  [708/315] 4 Claims
OG exemplary drawing
 
1. A computer implemented method of performing a filter function transforming a discrete time input signal X(k) into a discrete time output signal Y(k) according to a discrete time transfer function H(k) employing a programmable digital signal processor capable of performing a multiply-accumulate instruction of discrete time convolution of the form

OG Complex Work Unit Drawing
where: N is the number of terms of the convolution, H(n−k) is a discrete-time component of the transfer function, shifted by the current time step k, the method comprising:
if N is less than or equal to seven, performing a multiply-accumulate of X(k) and H(n−k) by performing a multiply-accumulate instruction on said programmable digital signal processor for all k of 0 to N; and
if N is greater than seven
performing a multiply-accumulate of X(k) and H(n−k) when X(k) and H(n−k) are overlapping by performing a multiply-accumulate instruction on said programmable digital signal processor, and
not performing a multiply-accumulate of X(k)H(n−k) when X(k) and H(n−k) are non-overlapping.