US 7,580,823 B2
Generation and use of integrated circuit profile-based simulation information
Nickhil Jakatdar, Los Altos, Calif. (US); Xinhui Niu, San Jose, Calif. (US); and Junwei Bao, Palo Alto, Calif. (US)
Assigned to Tokyo Electron Limited, Tokyo (Japan)
Filed on Nov. 09, 2006, as Appl. No. 11/595,358.
Application 11/595358 is a continuation of application No. 10/087069, filed on Feb. 28, 2002, granted, now 7,136,796.
Prior Publication US 2007/0118349 A1, May 24, 2007
Int. Cl. G06G 7/62 (2006.01)
U.S. Cl. 703—13  [703/14; 716/4] 20 Claims
OG exemplary drawing
 
1. A method of examination an integrated circuit (IC) structure formed on a semiconductor wafer, the method comprising:
obtaining a measured diffraction signal of the IC structure, the measured diffraction signal having been measured using an optical metrology device;
calculating diffraction signals using a metrology simulator;
storing the calculated diffraction signals and corresponding device attributes in a simulation data store embodied in a computer-readable storage medium, the device attributes including electrical and/or thermal properties of devices to be formed on the semiconductor wafer;
comparing the measured diffraction signal to the calculated diffraction signals stored in the simulation data store;
obtaining a best matching calculated diffraction signal from the simulation data store based on the comparison of the measured diffraction signal and the calculated diffraction signals stored in the simulation data store;
retrieving from the simulation data store the device attributes corresponding to the best matching calculated diffraction signal for examination the IC structure; and
outputting the retrieved device attributes.