| US 7,580,319 B2 | ||
| Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof | ||
| Kyoung-Ho Kim, Hwaseong-si (Korea, Republic of); Seong-Jin Jang, Seongnam-si (Korea, Republic of); Joung-Yeal Kim, Yongin-si (Korea, Republic of); and Sung-Hoon Kim, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Mar. 08, 2007, as Appl. No. 11/715,478. | ||
| Claims priority of application No. 10-2006-0021710 (KR), filed on Mar. 08, 2006; and application No. 10-2006-0092619 (KR), filed on Sep. 25, 2006. | ||
| Prior Publication US 2007/0211556 A1, Sep. 13, 2007 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.08 [365/233.1; 365/230.03] | 47 Claims |
| 42. An input latency control circuit, comprising:
a master circuit configured to generate a column control signal and a first write address control signal based on an internal
clock signal, a write command signal and a write latency signal;
at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address
signal in response to the column control signal and one of the first write address control signal and a second write address
control signal; and
at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address
signal in response to the column control signal and at least one of the first and second write address control signals.
|