US 7,580,315 B2
Card controlling semiconductor memory including memory cell having charge accumulation layer and control gate
Hidetaka Tsuji, Yokohama (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Jun. 25, 2007, as Appl. No. 11/767,865.
Claims priority of application No. 2006-182254 (JP), filed on Jun. 30, 2006.
Prior Publication US 2008/0002467 A1, Jan. 03, 2008
Int. Cl. G11C 8/00 (2006.01)
U.S. Cl. 365—230.03  [365/189.07; 365/236] 20 Claims
OG exemplary drawing
 
1. A card controller which writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time, the card controller comprising:
an arithmetic processing device which writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.