US 7,580,302 B2
Parallel threshold voltage margin search for MLC memory application
Wen Chiao Ho, Tainan (Taiwan); Chin Hung Chang, Tainan (Taiwan); Cheng-Chi Liu, Shulin (Taiwan); Kuen-Long Chang, Taipei (Taiwan); and Chun Hsiung Hung, Hsinchu (Taiwan)
Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan)
Filed on Oct. 23, 2006, as Appl. No. 11/551,974.
Prior Publication US 2008/0094891 A1, Apr. 24, 2008
Int. Cl. G11C 29/00 (2006.01)
U.S. Cl. 365—201  [365/185.22; 365/185.14] 19 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a memory array on the integrated circuit; and
logic on the integrated circuit configured to program a data set into a block of memory cells in the memory array; and iteratively read the block of memory cells at wordline voltages in a range of wordline voltages, calculating as-read sum code information indicating an as-read number of memory cells at the first programming level and an as-read number of memory cells at the second programming level for respective wordline voltages in the range; and to perform at least one of storing the as-read sum code information on the integrated circuit and supplying the as-read sum code information to an output on the integrated circuit.