| US 7,580,285 B2 | ||
| Semiconductor memory device using only single-channel transistor to apply voltage to selected word line | ||
| Hiroshi Nakamura, Fujisawa (Japan); and Kenichi Imamiya, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Kawasaki-shi (Japan) | ||
| Filed on Sep. 20, 2007, as Appl. No. 11/858,648. | ||
| Application 11/858648 is a continuation of application No. 11/374045, filed on Mar. 14, 2006, granted, now 7,286,402. | ||
| Application 11/374045 is a continuation of application No. 11/115364, filed on Apr. 27, 2005, granted, now 7,085,162, filed on Aug. 01, 2006. | ||
| Application 11/115364 is a continuation of application No. 10/607153, filed on Jun. 27, 2003, granted, now 6,912,157, filed on Jun. 28, 2005. | ||
| Application 10/607153 is a continuation of application No. 09/875944, filed on Jun. 08, 2001, granted, now 6,621,735, filed on Sep. 16, 2003. | ||
| Claims priority of application No. 2000-173715 (JP), filed on Jun. 09, 2000; and application No. 2000-330972 (JP), filed on Oct. 30, 2000. | ||
| Prior Publication US 2008/0019179 A1, Jan. 24, 2008 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.11; 365/230.06; 365/230.03] | 20 Claims |
| 1. A semiconductor memory device comprising:
a memory cell array in which memory cells are arranged in a matrix including a plurality of word lines and a plurality of
bit lines;
a plurality of blocks, each of the blocks including memory cells connected to a plurality of word lines;
a plurality of row decoder circuits selecting a first word line in the memory cell array and applying a voltage to the first
word line, one of the row decoder circuits being provided for a corresponding one of the blocks;
a plurality of first transistors having a first conductivity type, a source or a drain of each of the first transistors being
connected to a corresponding one of the word lines, two or more of the first transistors being included in each of the row
decoder circuits;
a plurality of second transistors having a second conductivity type opposite to the first conductivity type, a drain of the
second transistor being connected to a gate of the first transistor, at least one of the second transistors being included
in each of the row decoder circuits;
a plurality of well regions in each of which the second transistor is formed, the plurality of well regions having the first
conductivity type, one of the plurality of well regions corresponding to one of the blocks; and
a first well region included in the plurality of well regions;
wherein when at least one word line in a selected block is set to a first voltage which is higher than a power supply voltage,
the second transistor applies a second voltage to the gate of the first transistor, the second voltage is higher than the
first voltage, the first well region corresponds to one block, and the first well region is separated from well regions corresponding
to the other blocks.
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