| US 7,580,281 B2 | ||
| Flash memory device with write protection | ||
| Jin-Young Chun, Gangnam-gu (Korea, Republic of); Jae-Yong Jeong, Yongin-si (Korea, Republic of); and Chi-Weon Yoon, Seocho-gu (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jan. 07, 2008, as Appl. No. 11/969,969. | ||
| Claims priority of application No. 10-2007-0005259 (KR), filed on Jan. 17, 2007. | ||
| Prior Publication US 2008/0170436 A1, Jul. 17, 2008 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.04 [365/185.33] | 14 Claims |
| 1. A flash memory device comprising:
a memory cell array comprising a plurality of memory blocks;
control logic configured to control execution of a write operation directed to an identified memory block in the plurality
of memory block; and
a protection controller configured to generate a protection flag signal associated with the identified memory block, wherein
execution of the write operation by the control logic is enabled or disabled by the protection flag signal,
wherein the protection controller comprises:
a latch circuit comprising a plurality of latches, each corresponding to one of the plurality of memory blocks and storing
temporary protected/accessible data;
a cell array comprising a plurality of non-volatile memory cells storing, each corresponding to one of the plurality of memory
blocks and storing persistent protected/accessible data;
an address decoder receiving an address;
a write controller responsive to a received command and configured to alter the persistent protected/accessible data in relation
to the address; and
a latch controller responsive to a received command and configured to alter the temporary protected/accessible data in relation
to the address.
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