US 7,580,280 B2
Method and apparatus for a non-volatile memory device with reduced program disturb
Chung-Kuang Chen, Pan Chiao (Taiwan)
Assigned to Macronix International Co., Ltd., (Taiwan)
Filed on Sep. 27, 2007, as Appl. No. 11/862,903.
Application 11/862903 is a division of application No. 11/370368, filed on Mar. 08, 2006, granted, now 7,313,018.
Prior Publication US 2008/0055980 A1, Mar. 06, 2008
Int. Cl. G11C 16/24 (2006.01)
U.S. Cl. 365—185.02  [365/185.18; 365/185.25] 18 Claims
OG exemplary drawing
 
10. A method for reducing program disturb of a target memory cell in a memory cell array, comprising:
supplying a program voltage to a drain node of the target memory cell;
supplying a plurality of different initial shielding voltages to neighboring source/drain nodes in the memory cell array;
supplying a low voltage to a source node of the target memory cell; and
supplying a high voltage to a gate node of the target memory cell,
wherein the program voltage and each of the plurality of initial shielding voltages are non-zero voltages.