| US 7,580,053 B2 | ||
| Laser control circuit and image forming apparatus | ||
| Daisuke Ishikawa, Mishima (Japan); Koji Tanimoto, Shizuoka-ken (Japan); Kenichi Komiya, Kawasaki (Japan); and Yuji Inagawa, Numazu (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan); and Toshiba Tec Kabushiki Kaisha, Tokyo (Japan) | ||
| Filed on Apr. 04, 2008, as Appl. No. 12/62,627. | ||
| Application 12/062627 is a continuation of application No. 11/063544, filed on Feb. 24, 2005, granted, now 7,369,151. | ||
| Prior Publication US 2008/0186376 A1, Aug. 07, 2008 | ||
| Int. Cl. B41J 2/47 (2006.01); B41J 2/40 (2006.01); B41J 27/00 (2006.01); B41J 2/435 (2006.01) | ||
| U.S. Cl. 347—252 [347/255; 347/144; 347/241; 347/236] | 6 Claims |
| 1. A laser control circuit comprising:
a clock generation circuit which generates a reference clock signal;
a first synchronous circuit which includes a beam detection circuit detecting a light beam scanned in a main scanning direction
and supplying a horizontal synchronous signal, and which supplies a first clock synchronized with the horizontal synchronous
signal, on a basis of a reference clock signal from the clock generation circuit;
a delay circuit which supplies a delayed horizontal synchronous signal obtained by delaying the horizontal synchronous signal
by a half period of the first clock;
a second synchronous circuit which supplies a second clock synchronized with the delayed horizontal synchronous signal on
a basis of the reference clock signal;
an image data processing section which subjects input image data to image processing and which outputs first to fourth image
data in parallel;
a first pulse width modulation circuit which outputs a pulse having a width corresponding to the first image data as an odd-numbered
pixel with a left reference in accordance with the first clock;
a second pulse width modulation circuit which outputs a pulse having a width corresponding to the second image data as an
odd-numbered pixel with a right reference in accordance with the first clock;
a third pulse width modulation circuit which outputs a pulse having a width corresponding to the third image data as an even-numbered
pixel with the left reference in accordance with the second clock;
a fourth pulse width modulation circuit which outputs a pulse having a width corresponding to the fourth image data as an
even-numbered pixel with the right reference in accordance with the second clock;
a synthesis circuit which synthesizes the pulses output from the first to fourth pulse width modulation circuits; and
a laser which emits a light beam in accordance with the pulse synthesized by the synthesis circuit.
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