| US 7,579,886 B2 | ||
| Phase locked loop with adaptive phase error compensation | ||
| Michael M. Hufford, Catonsville, Md. (US); Eric Naviasky, Ellicott, Md. (US); and Tony Caviglia, Marriottsville, Md. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Dec. 07, 2006, as Appl. No. 11/608,213. | ||
| Prior Publication US 2008/0136532 A1, Jun. 12, 2008 | ||
| Int. Cl. H03L 7/06 (2006.01) | ||
| U.S. Cl. 327—156 [327/147] | 9 Claims |
| 1. For use with a phase lock loop (PLL) circuit that includes an oscillator that provides an oscillator output signal having
a frequency responsive to a control signal; a phase-frequency detector (PFD) that receives a reference signal and a feedback
signal and that provides pulse signals up and down indicative of phase error between the reference signal and the feedback
signal; a charge pump responsive to the pulses that provides an output current responsive to the pulses; a loop filter that
removes a high frequency constituent of the charge pump output and that provides the control signal in response to the charge
pump output current; and a multi-modulus divider circuit that receives a signal having the oscillator output signal frequency
and that provides the feedback signal having a time-averaged fractional division of the frequency of the oscillator output
signal, a method to further reduce phase error between the reference signal and the feedback signal comprising:
using the multi-modulus divider circuit to divide the feedback signal according to a multi-modulus pattern of divides;
during each of multiple respective divides in the pattern, determining an order of up and down pulses provided by the PFD
in response to a terminal count produced by the multi-modulus divider during such divides;
during each of multiple respective divides in the pattern,
determining a respective indication of a respective delay amount associated with the respective divide in the pattern;
wherein determining the respective indication of the delay amount includes, if the PFD provides the up and down pulses in
a first order in response to the terminal count produced by the multi-modulus divider circuit, then changing a respective
previously stored indication of a delay amount associated with the respective divide in the pattern so as to increase the
respective delay amount; and
wherein determining the respective indication of the delay amount further includes, if the PFD provides the up and down pulses
in a second order in response to the terminal count produced by the multi-modulus divider circuit, then changing a respective
previously stored indication of a delay amount associated with the respective divide in the pattern so as to decrease the
respective delay amount;
if determining the respective indication of the delay amount results in changing the respective previously stored indication,
then storing the changed indication in place of the previously stored indication;
delaying delivery to the PFD of a terminal count produced by the multi-modulus divider circuit during the respective divide
in the pattern based on the respective determined delay amount indication associated with that respective divide.
|