a first analog block, a second analog block, and a third analog block that are designed to provide substantially similar analog outputs when receiving substantially similar inputs, wherein the first analog block provides a first analog output, wherein the second analog block provides a second analog output, and wherein the third analog block provides a third analog output;

a first transconductor circuit including a first transistor pair and a second transistor pair, wherein the first transistor pair includes a first transistor connected in parallel with a second transistor, wherein the second transistor pair includes a third transistor connected in parallel with a fourth transistor, wherein a first load is connected between the first and second transistor pairs; and wherein the first analog output is connected to a gate of the first transistor, the second analog output is connected to a gate of the second and third transistors, and the third analog output is connected to a gate of the fourth transistor;

a second transconductor circuit including a third transistor pair and a fourth transistor pair, wherein the third transistor pair includes a fifth transistor connected in parallel with a sixth transistor, wherein the fourth transistor pair includes a seventh transistor connected in parallel with an eighth transistor, wherein a second load is connected between the third and fourth transistor pairs; and wherein the second analog output is connected to a gate of the fifth transistor, the first analog output is connected to a gate of the sixth and seventh transistors, and the third analog output is connected to a gate of the eighth transistor; and

wherein at least one output of the first transconductor circuit and the second transconductor circuit changes from a value of substantially zero to a non-zero value if one of the first, second, and third analog block outputs is impacted by a transient event.