| US 7,579,692 B2 | ||
| Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument | ||
| Fumiaki Matsushima, Chino (Japan); Tsutomu Ota, Chino (Japan); and Akira Makabe, Shiojiri (Japan) | ||
| Assigned to Seiko Epson Corporation, (Japan) | ||
| Filed on Oct. 30, 2007, as Appl. No. 11/980,126. | ||
| Application 11/980126 is a division of application No. 11/009995, filed on Dec. 10, 2004, granted, now 7,355,280. | ||
| Application 11/009995 is a division of application No. 09/945241, filed on Aug. 31, 2001, abandoned. | ||
| Claims priority of application No. 2000-267076 (JP), filed on Sep. 04, 2000. | ||
| Prior Publication US 2008/0073783 A1, Mar. 27, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 23/48 (2006.01) | ||
| U.S. Cl. 257—738 [257/737; 257/773; 257/E23.021; 257/E23.069] | 8 Claims |
| 1. A semiconductor device comprising:
a semiconductor chips;
a plurality of pads that is formed on a first surface of the semiconductor chip;
a metal layer that is disposed on one of the plurality of pads;
a plurality of leads; and
a soldering or brazing material disposed between the metal layer and one of the plurality of leads,
wherein the metal layer is bonded to the one of the plurality of leads through the soldering or brazing material,
wherein at least one depression is formed in a periphery of the metal layer in a cross-sectional view of the metal layer taken
parallel to the first surface of the semiconductor chip, and
the soldering or brazing material is located in the depression.
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