US 7,579,683 B1
Memory interface optimized for stacked configurations
Ohad Falik, Kfar Saba (Israel); and Aviv Melinovitch, Herzlia (Israel)
Assigned to National Semiconductor Corporation, Santa Clara, Calif. (US)
Filed on Sep. 03, 2004, as Appl. No. 10/934,113.
Claims priority of provisional application 60/583922, filed on Jun. 29, 2004.
Claims priority of provisional application 60/583919, filed on Jun. 29, 2004.
Claims priority of provisional application 60/583921, filed on Jun. 29, 2004.
Claims priority of provisional application 60/583923, filed on Jun. 29, 2004.
Claims priority of provisional application 60/583918, filed on Jun. 29, 2004.
Int. Cl. H01L 23/48 (2006.01)
U.S. Cl. 257—690  [257/678; 257/684; 257/691; 257/737; 711/157; 711/219] 20 Claims
OG exemplary drawing
 
1. A die, comprising:
a plurality of interconnection pads for connecting with a second die when the die and the second die are packaged together in a stacked manner, wherein the interconnection pads are disposed so that a layout of the interconnection pads on the die is invariable with respect to at least one of: a size of the second die and a number of data lines for carrying data signals between the die and the second die, the data lines including at least one default data line and two or more other data lines;
wherein the interconnection pads are disposed only along two mutually adjacent edges of the die, wherein at least one interconnection pad to be coupled to the at least one default data line is disposed on a first edge of the die, wherein two or more interconnection pads to be coupled to the two or more other data lines are disposed along a second edge of the die, and wherein the two or more other data lines are indexed in a sequential order and the two or more interconnection pads are disposed along the second edge of the die in the sequential order in which the two or more other data lines are indexed.