| US 7,579,671 B2 | ||
| Semiconductor device and manufacturing method thereof | ||
| Yukihiro Takao, Nitta-machi (Japan) | ||
| Assigned to Sanyo Electric Co., Ltd., Osaka (Japan) | ||
| Filed on May 24, 2004, as Appl. No. 10/851,638. | ||
| Claims priority of application No. 2003-147146 (JP), filed on May 26, 2003. | ||
| Prior Publication US 2005/0006783 A1, Jan. 13, 2005 | ||
| Int. Cl. H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—621 [257/711; 257/772; 257/E21.597] | 6 Claims |
| 1. A semiconductor device comprising:
a semiconductor die comprising a first surface and a second surface, a via hole being formed in the semiconductor die between
the first and second surfaces;
a pad electrode disposed on the first surface of the semiconductor die and covering one end of the via hole;
a first insulation layer formed on the second surface of the semiconductor die;
a wiring layer formed on the first insulation layer and electrically connected with the pad electrode through the via hole,
the wiring layer at least partially filling the via hole;
a protection layer covering the wiring layer; and
a conductive terminal formed on a portion of the wiring layer away from the via hole and electrically connected with the wiring
layer through a hole formed in the protection layer,
wherein the wiring layer does not extend to a lateral edge of the semiconductor die so as to expose the first insulation layer
at the lateral edge,
the protection layer does not extend to the lateral edge of the semiconductor die so as to expose the first insulation layer
on the second surface of the semiconductor die, and
the first insulation layer electrically insulates the wiring layer from the second surface of the semiconductor die.
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