| US 7,579,667 B2 | ||
| Bonded-wafer superjunction semiconductor device | ||
| Conor Brogan, Belfast (United Kingdom); Cormac MacNamara, Belfast (United Kingdom); Hugh J. Griffin, Newtownabbey (United Kingdom); and Robin Wilson, Belfast (United Kingdom) | ||
| Assigned to Icemos Technology Ltd., Belfast, Northern Ireland (United Kingdom) | ||
| Filed on Aug. 13, 2008, as Appl. No. 12/191,035. | ||
| Application 12/191035 is a division of application No. 11/466132, filed on Aug. 22, 2006, granted, now 7,446,018. | ||
| Claims priority of provisional application 60/710234, filed on Aug. 22, 2005. | ||
| Prior Publication US 2008/0315247 A1, Dec. 25, 2008 | ||
| Int. Cl. H01L 31/00 (2006.01); H01L 21/44 (2006.01) | ||
| U.S. Cl. 257—447 [438/667] | 6 Claims |
| 1. A bonded-wafer semiconductor device comprising:
a semiconductor substrate having first and second main surfaces opposite to each other;
a buried oxide layer disposed on at least a portion of the first main surface of the semiconductor substrate;
a multi-layer device stack having a first main surface and a second main surface, the multi-layer device stack including:
a first device layer of a first conductivity disposed on the buried oxide layer;
a second device layer of a second conductivity opposite to the first conductivity disposed on the first device layer;
a third device layer of the first conductivity disposed on the second device layer; and
a fourth device layer of the second conductivity disposed on the third device layer;
at least one trench formed in the first main surface of the multi-layer device stack, the at least one trench extending to
a first depth position in the multi-layer device stack;
at least one mesa proximate the first main surface of the multi-layer device stack being defined by the at least one trench,
the at least one mesa having a first sidewall and a second sidewall opposite the first sidewall;
a first anode/cathode layer disposed on a first sidewall of the multi-layer device stack; and
a second anode/cathode layer disposed on the second sidewall of the multi-layer device stack.
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