| US 7,579,640 B2 | ||
| Hybrid memory device | ||
| Yoko Kajita, Kanagawa (Japan); Ichiro Koiwa, Tokyo (Japan); Takao Kanehara, Tokyo (Japan); Kinya Ashikaga, Tokyo (Japan); and Kazuhide Abe, Tokyo (Japan) | ||
| Assigned to Oki Semiconductor Co., Ltd., Tokyo (Japan) | ||
| Filed on Sep. 19, 2005, as Appl. No. 11/228,188. | ||
| Claims priority of application No. 2004-276507 (JP), filed on Sep. 24, 2004; and application No. 2005-007077 (JP), filed on Jan. 14, 2005. | ||
| Prior Publication US 2006/0065917 A1, Mar. 30, 2006 | ||
| Int. Cl. H01L 27/115 (2006.01) | ||
| U.S. Cl. 257—295 [257/E27.104; 257/E21.663] | 5 Claims |
| 1. A hybrid memory device having a plurality of regions on a chip comprising:
a memory cell array region in which a plurality of memory cells each including a ferroelectric layer are formed in the form
of a matrix;
a logic circuit region including a logic circuit device;
an insulating layer formed on the memory cell array region and the logic circuit region;
first wiring units formed on the insulating layer and electrically connected to the memory cells in the memory cell array
region;
second wiring units formed on the insulating layer and electrically connected to the logic circuit device in the logic circuit
region;
a liner oxide layer formed on the insulating layer to cover the second wiring units over the logic circuit region, the liner
oxide layer does not cover the memory cell array region; and
a cover layer formed on the insulating layer to cover the first wiring units and the liner oxide layer.
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