a silicon substrate having a channel region;

a gate electrode formed on the silicon substrate corresponding to the channel region with a gate insulating film in between;

a first side wall insulating film formed on side walls of the gate electrode;

a second side wall insulating film formed on side surfaces of the first side wall;

a source extension region and a drain extension region formed from diffusion regions having a predetermined conductivity, said diffusion regions being formed in the silicon substrate on sides of the gate electrode to sandwich the channel region;

a source region and a drain region formed from diffusion regions having the predetermined conductivity, said diffusion regions being formed in the silicon substrate outside the second side wall insulating film and in contact with the source extension region and the drain extension region, respectively; and

a semiconductor mixed crystal layer formed in the silicon substrate outside the second side wall insulating film and epitaxially grown on the silicon substrate;

wherein

the semiconductor mixed crystal layer is formed from a SiGe mixed crystal when the predetermined conductivity is p-type, or from a SiC mixed crystal when the predetermined conductivity is n-type,

the semiconductor mixed crystal layer includes an impurity having the predetermined conductivity,

the semiconductor mixed crystal layer is grown to a height different from an interface between the silicon substrate and the gate insulating film,

the semiconductor mixed crystal layer has an extended portion between a bottom surface of the second side wall insulating film and an uppermost surface of the silicon substrate, said extended portion being in contact with a portion of one of the source extension region and the drain extension region, and

side surfaces of the semiconductor mixed crystal layer beneath the uppermost surface of the silicon substrate include facets formed so that the side surfaces of the source region and the drain region are a wedge shape facing inward.