| US 7,579,265 B2 | ||
| Method for manufacturing recess gate in a semiconductor device | ||
| Se-Aug Jang, Ichon-shi (Korea, Republic of); Heung-Jae Cho, Ichon-shi (Korea, Republic of); and Tae-Yoon Kim, Ichon-shi (Korea, Republic of) | ||
| Assigned to Hynix Semiconductor Inc., Kyoungki-do (Korea, Republic of) | ||
| Filed on Dec. 28, 2006, as Appl. No. 11/646,282. | ||
| Claims priority of application No. 10-2006-0096334 (KR), filed on Sep. 29, 2006. | ||
| Prior Publication US 2008/0081447 A1, Apr. 03, 2008 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—589 [257/E21.176] | 12 Claims |

| 1. A method for manufacturing a recess gate in a semiconductor device, the method comprising:
forming a device isolation structure on a substrate to define an active region;
forming a first hard mask pattern and a second hard mask pattern over the substrate;
forming an island-shaped mask pattern over the second hard mask pattern to cover facing ends of neighboring active regions
and the device isolation structure between the neighboring active regions:
etching the first hard mask using the island-shaped mask pattern and the second hard mask pattern as an etch barrier;
forming a recess pattern in the active region through an etching process using the first and second hard mask patterns as
an etch barrier to selectively expose at least a portion of the active region;
removing the first and second hard mask patterns;
forming a gate insulating layer over the substrate; and
forming a gate electrode over the gate insulating layer to cover at least the recess pattern,
wherein the second hard mask has a straight line pattern with spacing therebetween over the first hard mask.
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