| US 7,579,262 B2 | ||
| Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same | ||
| Jan Hoentschel, Dresden (Germany); Andy Wei, Dresden (Germany); Manfred Horstmann, Duemroehrsdorf-Dittersbach (Germany); and Thorsten Kammler, Ottendorf-Okrilla (Germany) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on Nov. 21, 2006, as Appl. No. 11/562,001. | ||
| Claims priority of application No. 10 2006 015 090 (DE), filed on Mar. 31, 2006. | ||
| Prior Publication US 2008/0090349 A1, Apr. 17, 2008 | ||
| Int. Cl. H01L 21/20 (2006.01); H01L 21/76 (2006.01); H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—478 [438/269; 438/413; 257/E21.601; 257/E21.403; 257/E21.632] | 23 Claims |
| 1. A method, comprising:
forming a first recess adjacent to a first gate electrode of a first transistor, said first gate electrode formed above a
substrate comprising a crystalline semiconductor layer;
forming a second recess adjacent to a second gate electrode of a second transistor;
epitaxially growing a first strained semiconductor material in said first recess while preventing growth of said first strained
semiconductor material in said second recess; and
epitaxially growing a second strained semiconductor material in said second recess and above said first strained semiconductor
material.
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