| US 7,579,256 B2 | ||
| Method for forming shallow trench isolation in semiconductor device using a pore-generating layer | ||
| Ho Seok Jeong, Dobong-gu (Korea, Republic of) | ||
| Assigned to Dongbu Electronics Co., Ltd., Seoul (Korea, Republic of) | ||
| Filed on Dec. 30, 2005, as Appl. No. 11/320,686. | ||
| Claims priority of application No. 10-2004-0117513 (KR), filed on Dec. 30, 2004. | ||
| Prior Publication US 2006/0148202 A1, Jul. 06, 2006 | ||
| Int. Cl. H01L 21/76 (2006.01) | ||
| U.S. Cl. 438—424 [438/296; 438/404; 257/E21.546] | 2 Claims |
| 1. A method for forming shallow trench isolation in a semiconductor device using a pore-generating layer, comprising:
forming a pad oxide, a pad nitride, and the pore-generating layer on an entire surface of a semiconductor substrate in successive
order;
etching the pore-generating layer, the pad nitride, the pad oxide and the substrate to form a trench in the substrate;
forming a trench oxide over the entire surface of the substrate by a CVD process to fill the trench, and forming a gas or
a liquid pore inside the trench oxide by liquefying or sublimating the pore-generating layer during the CVD process; and
removing the trench oxide in an active device area while retaining the trench oxide in the trench,
wherein the pore-generating layer being formed with a material that is inactive with the trench oxide.
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