| US 7,579,248 B2 | ||
| Resolving pattern-loading issues of SiGe stressor | ||
| Yu-Lien Huang, Jhubei (Taiwan); Jim Huang, Hsinchu (Taiwan); Ling-Yen Yeh, Hsinchu (Taiwan); and Hun-Jan Tao, Hsin-Chu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Feb. 13, 2006, as Appl. No. 11/352,588. | ||
| Prior Publication US 2007/0190730 A1, Aug. 16, 2007 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—300 [438/229; 257/346; 257/E21.619; 257/E21.634] | 23 Claims |
| 1. A method for forming a semiconductor structure, the method comprising:
providing a semiconductor substrate;
forming a first gate stack and a second gate stack over the semiconductor substrate;
forming recesses in the semiconductor substrate on opposing sides of the first gate stack and the second gate stack;
depositing SiGe in the recesses to form a first SiGe stressor on opposing sides of the first gate stack and a second SiGe
stressor on opposing sides of the second gate stack; and
etching the first and the second SiGe stressors to reduce a thickness of the first and the second SiGe stressors, wherein
the first SiGe stressor has a greater etching rate than the second SiGe stressor.
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