US 7,579,220 B2
Semiconductor device manufacturing method
Hideto Ohnuma, Kanagawa (Japan); Masaharu Nagai, Kanagawa (Japan); Mitsuaki Osame, Kanagawa (Japan); Masayuki Sakakura, Kanagawa (Japan); Shigeki Komori, Kanagawa (Japan); and Shunpei Yamazaki, Tokyo (Japan)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken (Japan)
Filed on May 16, 2006, as Appl. No. 11/383,694.
Claims priority of application No. 2005-148836 (JP), filed on May 20, 2005; and application No. 2005-150271 (JP), filed on May 23, 2005.
Prior Publication US 2006/0261336 A1, Nov. 23, 2006
Int. Cl. H01L 21/00 (2006.01)
U.S. Cl. 438—149  [438/151; 438/164; 257/E51.006; 257/E21.4] 24 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device comprising the steps of:
forming an insulating film on a semiconductor layer;
forming a first conductive film on the insulating film;
forming a second conductive film on the first conductive film;
forming a resist pattern on the second conductive film having end portions and a central portion that are thinner than remaining portions of the resist pattern from a cross-sectional view;
etching the second conductive film and the first conductive film to form a first conductive pattern from the first conductive film and a plurality of second conductive patterns from the second conductive film, the plurality of second conductive patterns being located apart from each other on the first conductive pattern;
doping the semiconductor layer with an impurity element by using the first conductive pattern and the plurality of second conductive patterns as masks to form a pair of first impurity regions in the semiconductor layer, both of the first impurity regions being located outside the first conductive pattern; and
doping the semiconductor layer with an impurity element by using the plurality of second conductive patterns as masks to form second impurity regions in the semiconductor layer, the second impurity regions being overlapped with the first conductive pattern.