| US 7,415,633 B2 | ||
| Method and apparatus for preventing and recovering from TLB corruption by soft error | ||
| Sujat Jamil, Chandler, Ariz. (US); and Hang Nguyen, Tempe, Ariz. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Apr. 06, 2004, as Appl. No. 10/818,766. | ||
| Application 10/818766 is a continuation of application No. 09/746765, filed on Dec. 22, 2000, granted, now 6,718,494. | ||
| Prior Publication US 2004/0193992 A1, Sep. 30, 2004 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 11/10 (2006.01) | ||
| U.S. Cl. 714—17 [714/805] | 21 Claims |
| 1. A method comprising:
identifying an error condition for a TLB entry including one or more first error checking bits;
stalling a processor pipeline stage responsive to identification of the error condition;
invalidating the TLB entry responsive to identification of the error condition; and
repeating the access of the TLB entry.
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