| US 7,415,567 B2 | ||
| Memory hub bypass circuit and method | ||
| Joseph M. Jeddeloh, Shoreview, Minn. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Apr. 04, 2006, as Appl. No. 11/398,018. | ||
| Application 11/398018 is a continuation of application No. 11/041071, filed on Jan. 21, 2005, granted, now 7,047,351. | ||
| Application 11/041071 is a continuation of application No. 10/222415, filed on Aug. 16, 2002, granted, now 7,149,874. | ||
| Prior Publication US 2006/0174070 A1, Aug. 03, 2006 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—5 [711/154] | 3 Claims |
| 1. A method of operating a memory hub coupled to a plurality of memory devices, the method comprising:
checking if the memory hub is servicing a memory request;
if the memory hub is not busy servicing a memory request, initially transmitting a portion of a received memory request from
the memory hub to the memory devices, and scheduling the remaining portion of the received memory request for subsequent transmission
from the memory hub to the memory devices; and
if the memory hub is busy servicing a memory request, scheduling the received memory request for subsequent transmission from
the memory hub to the memory devices.
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