US 7,414,875 B2
Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
Terry R. Lee, Boise, Id. (US); and Joseph M. Jeddeloh, Shoreview, Minn. (US)
Assigned to Mircon Technology, Inc., Boise, Id. (US)
Filed on Dec. 19, 2005, as Appl. No. 11/311,948.
Application 11/311948 is a continuation of application No. 10/434578, filed on May 08, 2003, granted, now 6,982,892.
Prior Publication US 2006/0215434 A1, Sep. 28, 2006
Int. Cl. G11C 11/401 (2006.01)
U.S. Cl. 365—63  [714/764; 714/773; 711/104; 711/170; 711/173; 711/211; 710/107; 710/305] 82 Claims
OG exemplary drawing
 
1. A memory module having a memory interface, comprising:
a plurality of memory devices organized into at least four memory ranks, each memory rank having a set of memory devices being electrically isolated from each other, at least one memory rank being located on a first side of the memory module and at least another memory rank being located on a second side of the memory module; and
at least four drivers, each respective drivers operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time.