| US 7,414,597 B2 | ||
| Plasma display panel driving circuit | ||
| Hak-Ki Choi, Cheonan (Korea, Republic of); Sang-Chul Kim, Cheonan (Korea, Republic of); Seung-Pil Mun, Cheonan (Korea, Republic of); Kwang-Ho Jin, Cheonan (Korea, Republic of); and Sun-Kyung Ahn, Asan (Korea, Republic of) | ||
| Assigned to Samsung SDI Co., Ltd., Suwon (Korea, Republic of) | ||
| Filed on Feb. 03, 2004, as Appl. No. 10/769,786. | ||
| Claims priority of application No. 10-2003-0016852 (KR), filed on Mar. 18, 2003. | ||
| Prior Publication US 2004/0183753 A1, Sep. 23, 2004 | ||
| Int. Cl. G09G 3/28 (2006.01) | ||
| U.S. Cl. 345—60 [345/41; 345/42; 345/62; 345/63; 345/204; 313/582; 313/586; 315/169.4] | 12 Claims |
| 1. A plasma display panel driving circuit for generating a ramp pulse for linearly increasing or decreasing a panel capacitor
voltage of a plasma display panel, comprising:
a transistor in which at least one parasitic capacitance is formed;
a negative feedback element coupled to the transistor, for performing negative feedback control on a voltage charged in the
parasitic capacitance so that the transistor may operate as a constant current source; and
a first capacitor coupled between a gate and an active node of the transistor, the first capacitor having a temperature characteristic
opposite to a temperature characteristic of the negative feedback element.
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