| US 7,577,947 B2 | ||
| Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects | ||
| Sreenivas Subramoney, Palo Alto, Calif. (US); Mauricio J. Serrano, San Jose, Calif. (US); Richard L. Hudson, Florence, Mass. (US); and Ali-Reza Adl-Tabatabai, Santa Clara, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 19, 2003, as Appl. No. 10/741,897. | ||
| Prior Publication US 2005/0138329 A1, Jun. 23, 2005 | ||
| Int. Cl. G06F 9/45 (2006.01) | ||
| U.S. Cl. 717—151 [711/213; 712/207] | 30 Claims |
| 1. A method comprising:
identifying one or more samples associated with cache misses using a performance monitoring unit in a processor system;
abstracting the one or more samples into a first linked data structure representing a parent delinquent object type determined
to be connected to a child delinquent object type by a first field of the parent delinquent object type, the first linked
data structure linked to a second linked data structure abstracted from the one or more samples when the parent delinquent
object type is determined to be linked to the child delinquent object type by a second field of the parent delinquent object
type different from the first field;
using the first linked data structure to identify one or more paths associated with high latency cache misses; and
identifying one or more prefetch points associated with the one or more paths at which to insert one or more prefetch instructions.
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