| US 7,577,927 B2 | ||
| IC design modeling allowing dimension-dependent rule checking | ||
| Evanthia Papadopoulou, Baldwin Place, N.Y. (US); and Daniel N. Maynard, Craftsbury Common, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Aug. 06, 2008, as Appl. No. 12/186,764. | ||
| Application 12/186764 is a continuation of application No. 11/926289, filed on Oct. 29, 2007. | ||
| Application 11/926289 is a continuation of application No. 10/708039, filed on Feb. 04, 2004, granted, now 7,404,164. | ||
| Prior Publication US 2009/0031265 A1, Jan. 29, 2009 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—1 [716/5; 716/7] | 12 Claims |
| 1. An integrated circuit (IC) modeling system comprising:
means for partitioning an edge of a shape in the IC design into a plurality of intervals; and
means for assigning at least one dimension to each interval;
wherein the partitioning means includes:
means for generating a core Voronoi diagram for the shape, the core Voronoi diagram being generated based on a L∞ metric, the L∞ metric defining a distance between two points in the shape as the maximum of a horizontal distance and a vertical distance
between the two points; and
means for partitioning the edge based on a core element for each vertex of the core Voronoi diagram, the core element being
one of a largest possible core element and a smallest possible core element; and
wherein in the case that the core element is the largest possible core element, the intervals are as large as possible, and
wherein in the case that the core element is the smallest possible core element, the intervals are as small as possible.
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