| US 7,577,882 B2 | ||
| Semiconductor integrated circuit including memory macro | ||
| Marefusa Kurumada, Kyoto (Japan); and Hironori Akamatsu, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Nov. 30, 2007, as Appl. No. 11/998,602. | ||
| Application 11/998602 is a division of application No. 10/300227, filed on Nov. 19, 2002, granted, now 7,451,363. | ||
| Claims priority of application No. 2001-354432 (JP), filed on Nov. 20, 2001. | ||
| Prior Publication US 2008/0091969 A1, Apr. 17, 2008 | ||
| Int. Cl. G11C 29/00 (2006.01) | ||
| U.S. Cl. 714—710 [714/711; 714/718] | 16 Claims |
| 1. A semiconductor integrated circuit comprising:
a plurality of memory macros and a redundant memory macro for repairing the plurality of memory macros,
each of the plurality of memory macros comprising:
a memory cell array connected to word lines and bit lines; and
a redundant circuit that has means for replacing a defective bit line of the memory cell array by an adjacent normal bit line
or a redundant bit line and outputs defect information to a redundant signal line;
the redundant memory macro comprising:
a redundant memory cell array connected to redundant word lines and the redundant bit line; and
a word line connection circuit that transmits a signal of a word line corresponding to a memory macro to be repaired to a
corresponding one of the redundant word lines with timing adjustment via a gate circuit, based on the defect information of
the redundant signal line, so as to block a signal of a word line corresponding to a normal memory macro with the gate circuit;
wherein the plurality of memory macros have a different number of word lines from each other, and a word line that is not
used in the redundant memory macro is connected to a ground potential.
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