a plurality of tiles, each tile comprising

a processor including a register file, with the processor configured to process multiple streams of instructions and to perform joint write operations,

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and

circuitry configured to couple the processor to the register file and to the switch of the same tile as the register file,

wherein the processor is configured to perform a joint write operation to have the circuitry send result data resulting from processing an instruction from a first of the streams of instructions to a storage location in the register file and to have the circuitry send the same result data to a port of the switch when the instruction targets the storage location in the register file and the port of the switch, wherein a portion of the instruction that targets the port of the switch uses only two bits to encode one of four output directions, and the processor is configured to issue an error signal if multiple of the streams of instructions target the same port of the switch in a single execution cycle, and the processor is configured to concurrently perform at least one additional operation to process an instruction from a second of the streams of instructions.