| US 7,577,819 B2 | ||
| Vector indexed memory unit and method | ||
| Rainer Buchty, Neuershausen (Germany); Nevin Heintze, Morristown, N.J. (US); and Dino P. Oliva, Maplewood, N.J. (US) | ||
| Assigned to Agere Systems Inc., Allentown, Pa. (US) | ||
| Filed on Oct. 05, 2007, as Appl. No. 11/973,078. | ||
| Application 11/973078 is a continuation of application No. 10/722100, filed on Nov. 25, 2003, granted, now 7,299,338. | ||
| Claims priority of provisional application 60/430749, filed on Dec. 04, 2002. | ||
| Prior Publication US 2008/0104364 A1, May 01, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01) | ||
| U.S. Cl. 711—220 [711/221] | 16 Claims |
| 1. A method for accessing at least one memory unit, wherein when the memory unit is based on an index vector comprising a
plurality of values, said method comprising the steps of:
concurrently performing an operation on individual ones of said plurality of index vector values stored in a single storage
register with a same base value to concurrently generate a plurality of memory addresses; and
concurrently accessing more than two of said plurality of memory addresses in said at least one memory unit, and
wherein when the memory unit is not based on an index vector, the single storage register is configured to concatenate the
plurality of index vector values into a single memory address.
|