a first processor; and

a simulator operable to represent elements including a second processor, using a plurality of simulated elements, and to simulate behaviors of said second processor,

said plurality of simulated elements comprising:

a memory element representing a memory operable to store executive instructions issued by said second processor and data treated by said second processor;

a register element representing a register in said second processor; and

a control element representing a controller operable to access at least one of said memory element and said register element,

wherein said simulator comprises:

a command input unit operable to analyze an entered command and to operate said plurality of simulated elements; and

a unit operable to check up on resource access in which said control element provides access to at least one of said memory element and said register element,

wherein said first processor is operated by said simulator,

wherein said second processor is a simulated target element of said simulator, and

wherein said unit operable to check up on said resource access comprises:

a resource information storage unit operable to store resource information, said resource information including a memory region range in said memory element, a read/write classification in said memory element, a register classification in said register element, and a read/write classification in said register element; and

a resource access-analyzing unit operable to analyze, with reference to said resource information, whether or not resource information includes a register classification and a read/write classification on said resource access, said resource access-analyzing unit being connected directly to said control element, said memory element, and said register element, thereby providing said unit operable to check up on said resource access with the ability to check up on said resource access in parallel with simulating behaviors of said second processor.