| US 7,577,054 B2 | ||
| Memory with word-line driver circuit having leakage prevention transistor | ||
| Toshikazu Nakamura, Kawasaki (Japan) | ||
| Assigned to Fujitsu Microelectronics Limited, Tokyo (Japan) | ||
| Filed on Oct. 31, 2007, as Appl. No. 11/979,237. | ||
| Claims priority of application No. 2006-295320 (JP), filed on Oct. 31, 2006. | ||
| Prior Publication US 2008/0137466 A1, Jun. 12, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.06 [365/185.23; 365/227; 365/228] | 14 Claims |
| 1. A semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection
thereof, the semiconductor memory comprising:
a word driver circuit that drives the word line and has a drive PMOS transistor and drive NMOS transistor which are connected
in series between a first node and a second node and each of which has a gate connected to a third node, said word line being
connected to a connection node of the two transistors;
a first voltage generating circuit that generates a first voltage; and
a second voltage generating circuit that generates a second voltage lower than said first voltage, wherein
said first voltage or said second voltage is applied to said third node, and said first voltage or second voltage is applied
to said first node; and
between said third node and the gate of the drive PMOS transistor, there is provided a leakage prevention NMOS transistor
having a gate applied with a prescribed voltage.
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