| US 7,577,041 B2 | ||
| Semiconductor memory device and writing method thereof | ||
| Yoshihiro Ueda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 17, 2007, as Appl. No. 11/736,379. | ||
| Claims priority of application No. 2006-174224 (JP), filed on Jun. 23, 2006. | ||
| Prior Publication US 2007/0297210 A1, Dec. 27, 2007 | ||
| Int. Cl. G11C 7/10 (2006.01) | ||
| U.S. Cl. 365—189.05 [365/149; 365/63] | 20 Claims |
| 1. A semiconductor memory device comprising:
a power supply circuit which generates a write current;
a write line to which a logic state is transferred;
a first pass transistor connected between the power supply circuit and the write line; and
a first register which connects to the write line, receives the logic state of the write line in an input state, stores the
received logic state in a storage state, and controls an on/off state of the first pass transistor on the basis of the stored
logic state.
|