a memory cell array of electrically erasable programmable non-volatile memory cells arrayed at intersections of local word lines and local bit lines;

a local row decoder configured to select one of the local word lines in accordance with an address signal; and

a global row decoder configured to select one of global word lines, which is to be connected to the local row decoder, in accordance with an address signal,

wherein the local row decoder includes

a first MOS transistor of a first conductivity type having one end connected to the local word line, the other end supplied with a first voltage, and a gate connected to the global word line, and

a second MOS transistor of a second conductivity type different from the first conductivity type having one end connected to the local word line, the other end supplied with a second voltage, and a gate connected to the global word line,

wherein the global row decoder is capable of independently selecting either a first global word line or a second global word line such that one is selected while the other is not selected, the first global word line being connected to the first MOS transistor and the second MOS transistor both connected to any one of the local word lines, and the second global word line being connected to the first MOS transistor and the second MOS transistor both connected to another adjacent local word line.