a memory device having a plurality of memory cells;

one or more inverters to invert data destined for the memory device;

a write inverted value logic to determine when to enable writing the inverted data to the memory device, wherein inverted data is to be written to one or more memory cells when enabled, wherein the write inverted value logic is to enable writing inverted data to a percentage of the memory cells, wherein the percentage is a dynamic parameter based on performance of the memory device, wherein the performance is measured by cache misses, and wherein the memory device is to invalidate the one or more memory cells when inverted data is written thereto.