| US 7,577,014 B2 | ||
| Semiconductor memory device | ||
| Yoshinobu Yamagami, Kyoto (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Jan. 08, 2007, as Appl. No. 11/650,482. | ||
| Claims priority of application No. 2006-054614 (JP), filed on Mar. 01, 2006. | ||
| Prior Publication US 2007/0206404 A1, Sep. 06, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01); G11C 7/10 (2006.01); G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—154 [365/189.08; 365/191; 365/193; 365/196; 365/226] | 26 Claims |
| 1. A semiconductor memory device, comprising:
a memory cell including a flip-flop; and
a memory cell power supply circuit for supplying a high cell power supply voltage and a low cell power supply voltage with
a lower voltage potential than the high cell power supply voltage to the memory cell,
wherein the memory cell power supply circuit supplies:
a predetermined first power supply voltage supplied as the low cell power supply voltage in a case where the low cell power
supply voltage is supplied in a data read cycle and in a case where data is not written to the memory cell to which the low
cell power supply voltage is supplied in a write cycle, and
a second power supply voltage higher than the first power supply voltage supplied as the low cell power supply voltage in
a case where data is written to the memory cell to which the low cell power supply voltage is supplied in a write cycle,
wherein:
the first power supply voltage is output in response to a write disable control signal or a column non-select signal; and
the second power supply voltage is output in response to a write enable control signal and a column select signal.
|