| US 7,577,011 B2 | ||
| Optimization of ROM structure by splitting | ||
| Prasad Avss, Bangalore (India); and Ravi Pathakota, Proddatur (India) | ||
| Assigned to Agere Systems Inc., Allentown, Pa. (US) | ||
| Filed on Jan. 15, 2007, as Appl. No. 11/623,218. | ||
| Application 11/623218 is a continuation in part of application No. 11/580786, filed on Oct. 13, 2006. | ||
| Prior Publication US 2008/0104566 A1, May 01, 2008 | ||
| Int. Cl. G11C 17/00 (2006.01); G11C 8/00 (2006.01); G06F 12/00 (2006.01) | ||
| U.S. Cl. 365—94 [365/230.01; 365/189.011; 711/170; 711/171; 711/102] | 7 Claims |
| 1. A read-only memory (ROM) comprising:
Q input address lines for supplying an address;
P output bit lines for supplying a P-bit data word according to the first address; and
N memory cells C1 to CN, where N>1, and each memory cell Ci comprises:
Wi word lines respectively electrically coupled to Bi bit lines according to a dataset to be stored within the ROM, wherein 1<Bi<P; and
a decoder Di coupled to the Q input lines and adapted to assert one of the Wi word lines according to the first address;
wherein for at least one of the memory cells Ci, the corresponding number of word lines Wi is less than 2Q; and
wherein the P-bit data word is obtained from the bit lines of the memory cells.
|