| US 7,577,010 B2 | ||
| Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays | ||
| Nicolas Nagel, Dresden (Germany); and Josef Willer, Riemerling (Germany) | ||
| Assigned to Qimonda AG, Munich (Germany) | ||
| Filed on Mar. 14, 2007, as Appl. No. 11/686,211. | ||
| Prior Publication US 2008/0225587 A1, Sep. 18, 2008 | ||
| Int. Cl. G11C 5/06 (2006.01) | ||
| U.S. Cl. 365—63 [365/51; 365/72; 365/182; 365/230.06] | 28 Claims |
| 1. An integrated circuit, comprising:
a cell array plane comprising a cell array having a plurality of cells, at least one of the plurality of cells coupled to
an address line;
a signal distribution plane monolithically integrally formed with the cell array plane and comprising a signal line distributing
a signal therealong; and
a switching plane monolithically integrally formed with and coupled between the cell array plane and the signal distribution
plane, the switching plane comprising a first switch having a first port coupled to the signal line in the signal distribution
plane, a second port coupled to the address line in the cell array plane, and a control port controlling a conduction state
of the first switch, the first switch being operable to selectively conduct a signal between the signal line and the address
line.
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