| US 7,576,964 B2 | ||
| Overvoltage protection circuit of output MOS transistor | ||
| Akihiro Nakahara, Kanagawa (Japan) | ||
| Assigned to NEC Electronics Corporation, Kanagawa (Japan) | ||
| Filed on Sep. 24, 2004, as Appl. No. 10/948,192. | ||
| Claims priority of application No. 2003-340848 (JP), filed on Sep. 30, 2003. | ||
| Prior Publication US 2005/0068705 A1, Mar. 31, 2005 | ||
| Int. Cl. H02H 3/20 (2006.01); H02H 9/04 (2006.01); H02H 9/00 (2006.01); H02H 3/22 (2006.01); H01C 7/12 (2006.01); H02H 1/00 (2006.01); H02H 1/04 (2006.01); H02H 9/06 (2006.01) | ||
| U.S. Cl. 361—91.1 [361/56; 361/111; 361/118] | 9 Claims |
| 1. An overvoltage protection circuit for a circuit of an output MOS transistor and a load connected in series between a first
power supply and a second power supply, comprising:
a drain and source of said output MOS transistor connected to said first power supply and load respectively;
a dynamic clamping circuit connected with a gate of said output MOS transistor;
a control switch connected between said first power supply and said dynamic clamping circuit; and
a surge detecting circuit configured to monitor voltage of said first power supply and turn off said control switch such that
said dynamic clamping circuit does not operate when the voltage of said first power supply increases to a voltage higher than
a predetermined voltage, and
wherein said first power supply has a positive potential relative to said second power supply, said output MOS transistor
connected to said first power supply and said load connected to said second power supply.
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