determining a video control signal received at a video subsystem of an integrated circuit is a valid video control signal in response to a transition of the video control signal from a first logic state to a second logic state occurring at a predetermined time range;

determining the video control signal is an invalid video control signal in response to a transition of the video control signal from the first logic state to the second logic state not occurring at the predetermined time range;

in response to determining a valid video control signal is received, providing a delayed representation of the video control signal to an input of a display engine, wherein the delayed representation represents the video control signal delayed by a first predetermined amount and comprises a first pulse edge provided to the display engine at a first time; and

in response to determining an invalid video control signal is received, providing an alternate video control signal to the input of the display engine, the alternate video signal comprising a second pulse edge provided at approximately the first time.