| US 7,576,668 B2 | ||
| Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) | ||
| Anand Hariraj Udupa, Richardson, Tex. (US); Vikas Kumar Sinha, Karnataka (India); Nitin Agarwal, Karnataka (India); Visvesvararaya A. Pentakota, Karnataka (India); and Sandeep Oswal, Karnataka (India) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Nov. 02, 2007, as Appl. No. 11/934,611. | ||
| Application 11/934611 is a division of application No. 11/160859, filed on Jul. 13, 2005, granted, now 7,310,058. | ||
| Prior Publication US 2008/0055129 A1, Mar. 06, 2008 | ||
| Int. Cl. H03M 1/00 (2006.01) | ||
| U.S. Cl. 341—122 [341/118; 341/120; 341/155; 341/161; 341/162] | 9 Claims |
| 1. An analog to digital converter (ADC) comprising:
a first sample and hold amplifier (SHA) receiving an input signal and providing an amplified version of the input signal on
a first path;
a second SHA receiving the input signal and also providing an amplified version of the input signal on a second path;
a stage of an ADC generating a sub-code from the input signal, the stage including:
a flash ADC sampling the input signal on the first path from the first SHA, and generating a sub-code representing a strength
of the input signal; and
a DAC-Subtractor circuit sampling the input signal on the second path from the second SHA, the first circuit generating an
amplified residue signal for processing by a next stage that forms at least a portion of the ADC.
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