| US 7,576,629 B2 | ||
| Semiconductor device having signal line and reference potential planes separated by a vertical gap | ||
| Tetsu Nagamatsu, Kawasaki (Japan); and Yuuichi Hotta, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, (Japan) | ||
| Filed on Dec. 07, 2005, as Appl. No. 11/297,042. | ||
| Claims priority of application No. 2004-356735 (JP), filed on Dec. 09, 2004. | ||
| Prior Publication US 2006/0146135 A1, Jul. 06, 2006 | ||
| Int. Cl. H01P 3/08 (2006.01) | ||
| U.S. Cl. 333—247 [333/33] | 6 Claims |
| 3. A semiconductor device comprising:
a signal line;
a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential
plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be
added to the signal line;
a semiconductor chip, wherein the signal line and the reference potential plane are electrically connected to the semiconductor
chip; and
a wiring board on which the semiconductor chip is mounted, wherein the signal line and the reference potential plane are disposed
on the wiring board,
wherein the reference potential plane comprises a first reference potential plane and a second reference potential plane which
is disposed above the first reference potential plane and separated from the first reference potential plane, the discontinuous
region comprises a gap between the first and second reference potential planes.
|