a transmission circuit including resistance-based means for effecting clock deskew associated with the transmission circuit, said resistance-based means including distributed resistive loads to generate clock signals with variable delay, said transmission circuit including: (i) serially connected transmission gates defining an input end and an output end, wherein the serially connected transmission gates are adapted to receive an input clock signal at the input end, and (ii) a plurality of control transmission gates in communication with the transmission circuit associated with transmission of the input clock signal from the input end to the output end, and

wherein each of the plurality of control transmission gates is adapted to receive a control signal,

wherein a selected control transmission gate is turned on by delivery of a control signal thereto;

wherein an output clock signal is sampled from a node associated with the selected control transmission gate, thereby controlling clock skew through resistance variation associated, at least in part, through delivery of the control signal to the selected control transmission gate and sampling of the output clock signal from the node associated therewith;

wherein the node associated with each control transmission gate contains a different copy of the input clock signal;

wherein the copy of the input clock signal at a given control transmission gate demonstrates incremental delay moving from the input end to the output end; and

wherein delay adjustment of the clock signal is accomplished by shifting the control signal from a first control transmission gate to a second control transmission gate.