| US 7,576,566 B2 | ||
| Level-conversion circuit | ||
| Kyoichi Nagata, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc, Tokyo (Japan) | ||
| Filed on Sep. 06, 2007, as Appl. No. 11/850,748. | ||
| Application 11/850748 is a division of application No. 11/087688, filed on Mar. 24, 2005, granted, now 7,288,963. | ||
| Claims priority of application No. 2004-086757 (JP), filed on Mar. 24, 2004. | ||
| Prior Publication US 2007/0296482 A1, Dec. 27, 2007 | ||
| Int. Cl. H03K 19/0175 (2006.01) | ||
| U.S. Cl. 326—81 [326/86] | 12 Claims |
| 1. A level-conversion circuit, comprising:
a PMOS-driver control unit;
an NMOS-driver control unit;
a PMOS-side power-source control unit;
an NMOS-side power-source control unit;
an output unit; and
an output-feedback unit that outputs an inverted output signal, wherein,
each of the PMOS-driver control unit and the NMOS-driver control unit inverts a small-amplitude input signal and transmits
the inverted small-amplitude input signal to the output unit, and
each of the PMOS-side power-source control unit and the NMOS-side power-source control unit establishes electrical continuity
between the output unit and at least one power source upon receiving the inverted output signal so that the output unit transmits
a large-amplitude output signal.
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